1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that functions as a differential programmable device, a programming method and programming system therefore.
2. Description of Related Art
FIG. 1 is an example of a structure of a typical CPLD (Complex Programmable Logic Device). In such a CPLD, the device is programmed by connecting/disconnecting interconnections (VIA). The interconnections are nonvolatile. Also, upon re-programming, the device is initialized and rewritten. In this case, there is almost no difference in programming time between a first programming and a second or a subsequent programming.
In conjunction with the above technique, a method of configuring a logic device array is disclosed in Japanese Patent Application Publication (JP 2001-504958A: first conventional example). In this first conventional example, under the assumption that a state of a device is always controlled and recognized by a host, a design database is generated by arranging and routing a logic circuit. The design database is accessed to edit the configuration of a logic cell generated by the arrangement and routing operations. On the basis of the edition, a partial configuration bit stream including only a bit string is generated to achieve the edited logic cell. The partial configuration bit stream is downloaded to a gate array. This allows the gate array to be partially configured. In an alternative example, a system according to this first conventional example includes a software utility that an application program is executed in a system including a programmable gate array to permit an on-the-fly array to be re-configured. The utility includes a routine in which a design is edited in response to an external situation detected during an actual time. This approach eliminates the necessity to provide the predetermined alternative design, and allows an application to make a determination by itself.
FIG. 2 is an example of a procedure in a conventional operation method of the device. In this example, the assumption is that the device state has been already known.
In this operation method, an initial design is inputted (Step P1). Then, on the basis of the inputted initial design, arrangement and routing of a logic circuit are performed (Step P2), and on the basis of a performing result, a first design database is generated (Step P3), and a first configuration bit stream is generated (Step P4). At this time, the first configuration bit stream is downloaded (Step P5a) or stored in a FPGA (Field Programmable Gate Array) (Step P5b). In the case where the initial design is edited (Step P6), the arrangement and routing of the logic circuit are performed on the basis of the edited initial design (Step P7). On the basis of a performing result, a second design database is generated (Step P8), and a second configuration bit stream is generated (Step P9). Then, as a difference between the first and second configuration bit streams, a partial bit stream is generated (Step P10). At this time, the partial bit stream may be adapted to be downloaded to the FPGA (Step P11). Whether or not the partial bit stream is downloaded to the FPGA is optional. If the initial design is further edited, the above-described edition is repeated (Step P12).
However, in a highly integrated programmable device, the number of interconnections increases, and therefore a programming time increases. An estimate of the programming time is preferably measured on the order of msec (milliseconds). In particular, if it takes a long time to program one of the interconnections, the above problem becomes obvious.
The method of differential programming in FIG. 2 cannot be used for a case where a state of a device is unknown, or devices in a plurality of states are mixed.